The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the inventors hereof, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted to be prior art against the present disclosure.
Data memory elements such as static random-access memory (SRAM) can use two types of 1-Read/1-Write memory bit cells. A first type of bit cells may focus on optimizing area, rather than performance, which may use an 8-transistor (8T) single-ended bit line read scheme. Another type may focus on performance at the cost of a larger area, which may use an 8T differential bit line read scheme with larger transistors. In advanced semiconductor process nodes, the performance-area trade-off may incur performance drawbacks that affect yield and reliability of the memory unit. Specifically, when a fin field effect transistor (Fin-Fet) is used, the allowed channel lengths and the channel widths may be constrained and may change in increments by the number of fins. Thus the performance-area trade-off can be significant.
For a 2-read/write or dual-port (SR2P) memory cell, each of the two ports may perform both a read operation and a write operation. However, a SR2P may be susceptible to interactions between the two ports, and write-induced-read failures, read-induced-write failures read-induced-read failures, and both-ports-ON-induced disturb failures.
For multi-port memory cells, maintaining a good write/read/stability margin can be difficult, which may result in larger size of individual transistors, a greater overall leakage power, and greater risk of port-to-port interaction related failures.